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Silicon Labs /SiM3_NRND /SIM3L168_A /ACCTR_0 /DBCONFIG

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Interpret as DBCONFIG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LDBTH0HDBTH0 (DISABLED)INTEGDCEN 0 (LOW)INTEG0 0 (LOW)INTEG1

INTEG1=LOW, INTEGDCEN=DISABLED, INTEG0=LOW

Description

Pulse Counter Debounce Configuration

Fields

LDBTH

Integrator Low Debounce.
HDBTH

Integrator High Debounce.
INTEGDCEN

PC Integrator Disconnect Enable.

0 (DISABLED): Connect integrator to 24 bit counter state machine logic.

1 (ENABLED): Disconnect the integrators from the IN0 and IN1 inputs.
INTEG0

PC Integrator 0 Output.

0 (LOW): The integrator 0 output is low.

1 (HIGH): The integrator 0 output is high.
INTEG1

PC Integrator 1 Output.

0 (LOW): The integrator 1 output is low.

1 (HIGH): The integrator 1 output is high.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data